Xiaomi O100 AI chip

Uses W2W hybrid bonding on 6nm process that stacks 2 memory wafers on top of a NPU wafer. 1.4 µm HB pitch & 0.7 µm diameter allowing for 2.58m physical interconnect pts. 14 NPU cores, 330 TOPS & 1.22 TB/s high speed memory This bonding process seems to use the same advanced packaging partner as HW (likely JCET or Tongfu) Also interesting it uses 6nm process I don't think SMIC N+3 is mature enough for larger die yet, so this is likely TSMC or Samsung. Note that w/ hybrid bo — via @tphuang

Advanced packaging breakthrough signals Xiaomi's AI chip competitiveness, validated by 330 TOPS and 1.22 TB/s specs.