SK hynix looks beyond HBM to tackle AI memory bottlenecks

What happened: SK hynix is expanding its AI memory strategy beyond high-bandwidth memory, developing 3D stacked DRAM and high-bandwidth flash to address data bottlenecks as AI shifts toward complex inference workloads, per a SEDEX 2026 keynote by CDO Ahn Hyun. Key numbers: AI infrastructure performance requirements Why it matters: SK hynix plans to optimize the entire memory hierarchy rather than individual chips, and Ahn stressed industry standards for HBF plus cooperation with global partners. SEDEX 2026 featured an Nvidia Vera Rubin superchip and an HBM wafer signed by Jensen Huang.

SK hynix is expanding its AI memory strategy beyond high-bandwidth memory, developing 3D stacked DRAM and high-bandwidth flash to address data bottlenecks as AI shifts toward complex inference workloads, per a SEDEX 2026 keynote by CDO Ahn Hyun.

SK hynix plans to optimize the entire memory hierarchy rather than individual chips, and Ahn stressed industry standards for HBF plus cooperation with global partners. SEDEX 2026 featured an Nvidia Vera Rubin superchip and an HBM wafer signed by Jensen Huang.